The invention relates to the measurement of the thickness of an interlevel dielectric within semiconductor chips. Specifically, the invention involves a method and apparatus for accurately measuring the interlevel dielectric thickness, after chemical-mechanical planarization, above a plurality of structures within a complex semiconductor chip, such as a non-volatile memory chip.
In the fabrication of semiconductor chips today, it is important that insulating layers have a smooth surface topography. For example, having a smooth surface topography provides increased resolution and relieves depth of focus constraints in photolithography. Planarized surfaces on dielectric layers are often obtained using a process known as chemical-mechanical planarization (CMP). This process planarizes a dielectric layer formed, for example, over gate structures in a semiconductor chip thus facilitating easier fabrication.
In addition to controlling the smoothness or degree of planarization of the dielectric layer, it is often imperative that the thickness of an interlevel dielectric formed over gate structures also be strictly controlled. The thickness of the dielectric layer above chip components such as gate structures can have a direct effect on performance, especially in multi-level chips. If the dielectric layer, after chemical-mechanical planarization, is too thin, the electrical characteristic of the underlying structures is altered. If the layer is too thick, it will adversely affect the successful performance of subsequent process steps, such as contact hole etching. Also, the tolerances defining acceptable dielectric layer thicknesses are often very strict.
One technique for measuring post-chemical-mechanical planarization thickness of an interlevel dielectric appears to provide acceptable results when used with relatively simple semiconductor chips. Such chips tend to comprise either only one type of structure or multiple, but very similar, types of structures. Typically, a monitor box is formed directly on the chip at the same time and by the same process as the other structures on the chip. Thus, the monitor box represents a structure of the type used in the chip in both height and material constitution. The monitor box provides a location on which measurements of the thickness of a subsequently formed and planarized dielectric layer can be made.
The present invention provides a method and apparatus for accurately measuring the interlevel dielectric thickness, after chemical-mechanical planarization, above a plurality of structures within a complex semiconductor chip. The existing technique as described above has been found, by the inventors, to be imprecise when applied to the fabrication of complex semiconductor chips. Complex chips contain a plurality of differing structure types. These structure types are subjected to different process steps and thus, tend to have different heights and constitutions. An example of such a complex chip is a nonvolatile memory, such as an erasable programmable read-only memory (EPROM) or a non-volatile random access memory (NVRAM), which has a single polysilicon structure in its periphery area and a dual polysilicon structure in its core area.
The inventors have found that due, in part, to the large differences between the structures within these complex chips, the dielectric layer formed over such structures tends to have not insubstantial variations in thickness. Such variations render the post-CMP dielectric thickness measurement technique described above imprecise and prone to providing incomplete or misleading information on which the determination of chip acceptability is often based. The technique of the present invention overcomes the above identified problem associated with complex semiconductor chips.
Disclosed herein is a method of measuring the thickness of a dielectric layer above a plurality of structures of differing types within a semiconductor chip. The method comprises the steps of: forming a plurality of monitor boxes on a semiconductor chip such that each of said plurality of monitor boxes represents a structure type within the semiconductor chip and has substantially the same step height as one of a plurality of differing structure types; forming a dielectric layer over the semiconductor chip; and measuring a thickness of the dielectric layer above at least one of said plurality of monitor boxes, wherein the thickness represents a thickness of the dielectric layer above a structure of the structure type represented by the monitor box.
In the method of the present invention, the step of forming a plurality of monitor boxes can also comprise forming each of the plurality of monitor boxes by using substantially the same process as used in forming the structure type represented by the monitor box. Also, the step of forming a dielectric layer can comprise the step of performing chemical-mechanical planarization of the dielectric layer. Furthermore, the method of the present invention can include the step of locating at least one of said plurality of monitor boxes in a scribe line area of the semiconductor chip or in proximity to a structure of the structure type represented by the monitor box.
Also disclosed herein is a semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a plurality of structures of differing types located on a surface within the semiconductor chip; and a plurality of monitor boxes, located on the surface within the semiconductor chip, upon which measurements of dielectric thickness can be made, wherein each of the plurality of monitor boxes represents a structure type within the semiconductor chip.
Further disclosed is a non-volatile memory semiconductor chip that allows for accurate dielectric thickness measurements. The chip comprises: a core area comprising at least one first structure type; a periphery area comprising at least one second structure type; a core area monitor box, upon which measurements of dielectric thickness can be made, having substantially the same layers and substantially the same step height as the first structure type; and a periphery area monitor box, upon which measurements of dielectric thickness can be made, having substantially the same layers and substantially the same step height as the second structure type.
Other features and advantages of the present invention will become apparent to those skilled in the art from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration and not limitation. Many changes and modifications within the scope of the present invention may be made without departing from the spirit thereof, and the invention includes all such modifications.